SAF784X datasheet(28/93 Pages) NXP

28 / 93 page

SAF784X_2

Product data sheet

Rev. 02 — 9 May 2008

28 of 93

NXP Semiconductors

SAF784x

One chip CD audio device with integrated MP3/WMA decoder

6.5.5.2

Bit detector

The bit detector block contains the slice-level circuitry, a noise ﬁlter to limit HF EFM signal

noise contribution, an equalizer, a zero-transition detector, a run-length push-back circuit,

a digital PLL and jitter measurement logic.

All processing is performed on the bit clock, and bandwidths are proportional to the

channel bit rate. To achieve this, RF data is resampled from the system clock domain to

the bitclk domain by making use of a sample-rate convertor. Blocks can be conﬁgured

under microcontroller control and are described in detail in the next paragraphs.

Noise ﬁlter: The digital noise ﬁlter runs on the channel bit clock frequency fclk(bit)ch. It

limits the bandwidth of the incoming signal to 1

⁄

4 of the channel bit clock frequency.

Passband: 0

× f

clk(bit)ch to 0.22 × fclk(bit)ch (Hz)

Stop-band: (0.28

× f

clk(bit)ch) to (fclk(bit)ch − 0.28 × fclk(bit)ch) (Hz)

Rejection:

−28 dB

Slice-level determination: The slice-level determination circuit compensates for the

incoming signal asymmetry component. Bandwidth of the slice-level determination circuit

is programmable via register SlicerBandwidth. Also the higher bandwidths for use after a

defect (see Section “Defect detector” on page 26) are programmed in this register. The

bandwidth is proportional to the channel bit clock frequency. The slice level, or asymmetry,

can be read back via register SlicerAssym.

Equalizer: In the bit detection circuit, a programmable equalizer is used to boost the high

frequency content of the incoming signal.

The equalizer includes an integral ﬁve-tap presentable, asymmetrical equalizer. The

equalizer block diagram is given in Figure 16.

Fig 15. Bit detector block diagram

001aag319

clocked on

PLL clock

multiplex

to demodulator

Meas1

jitter value

from

signal

conditioning

−

PLL frequency

slice level

SRC

NOISE

FILTER

DIGITAL

PLL

RMS

JITTER

MEASUREMENT

RL2

PUSHBACK

DIGITAL

EQUALIZER

SLICE

LEVEL

DETERMINE

ZERO

TRANSITION

DETECT

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