ST7540 datasheet(22/44 Pages) STMICROELECTRONICS

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Functional description

ST7540

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6.5.2

Control register access

The communication with ST7540 Control Register is always synchronous. The access is

achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus

REG_DATA Line.

With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control

edge).

In Normal Control Register mode (Control Register bit 21 = ”0”, see Table 12) if more than

24 bits are transferred to ST7540 only latest 24 bits are stored inside the Control Register. If

less than 24 bits are transferred to ST7540 the Control Register writing is aborted.

In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations

(for example because of surge or burst on mains), in Extended Control Register mode

(Control Register bit 21 = ”1” see Table 12) exactly 24 or 48 bits must be transferred to

ST7540 in order to properly write the Control Register, otherwise writing is aborted. If 24 bits

are transferred, only the first 24 Control Register bits (from 23 to 0) are written.

With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port.

The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register

mode 24 bits are transferred from ST7540 to the Host. In Extended Control Register mode

24 or 48 bits are transferred from ST7540 to the Host depending on content of Control

transferred, see Table 12).

Figure 9.

Data reception ➨ control register read ➨ data reception timing diagram

Figure 10. data reception ➨ control register write ➨ data reception timing diagram

TCC

TDS

TDH

TCR

TDS

TDH

TCC

CLR_T

RxD

REG_DATA

RxTx

D03IN1404

BIT23

BIT22

TCC

TCR

TDH

TDS

TCC

CLR_T

RxD

RxTx

TxD

REG_DATA

D03IN1403

BIT23

BIT22

TSTH

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