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EB632 数据表(PDF) 23 Page - Freescale Semiconductor, Inc |
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EB632 数据表(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 112 page ![]() HDI16 Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 Freescale Semiconductor 23 ICR is a read/write control register that allows the use of bit manipulation instructions on control register bits. The host processor uses the ICR to control the HDI16 interrupts and flags. The SC140 core cannot access the ICR. The HPCR[DMA] bit and the HCR[HICR] bit control the function of the ICR bits. ICR Mask Set 2K42A Interface Control Register (DMA = 0, HICR = 0) 0x0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 — HF0 HF1 — INIT HDM HF2 HF3 HDRQ TREQ RREQ Type R/W R R/W Reset See Table 18 on page 25 ICR Mask Set 2K42A Interface Control Register (DMA = 1, HICR = 0) 0x0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 — HF0 HF1 — INIT HDM HF2 HF3 — Note 1 Note 2 Type R/W R R/W R/W Reset See Table 18 on page 25 Notes: 1. HDM0 when read, TREQ when written 2. HDM0 when read, RREQ when written Table 17. Mask Set 2K42A ICR Bit Descriptions Name Description — 0–4 Reserved. Write to zero for future compatibility. HF0 5 Host Flag 0 A general-purpose flag for host-to-core communication. The host processor can set or clear HF0. HF0 is reflected in the HSR on the core side of the HDI16. HF1 6 Host Flag 1 A general-purpose flag for host-to-core communication. The host processor can set or clear HF1. HF1 is reflected in the HSR on the core side of the HDI16. — 7 Reserved. Write to zero for future compatibility. INIT 8 Force Initialization Used by the host processor to force initialization of the HDI16 hardware (which may or may not be necessary, depending on the software design of the interface). During initialization, the HDI16 transmit and receive control bits are configured. The type of initialization performed when the INIT bit is set depends on the state of TREQ and RREQ in the HDI16. The INIT command, which is local to the HDI16, conveniently configures the HDI16 into the desired data transfer mode. The effect of the INIT command is described in Table 19. When the host sets the INIT bit, the HDI16 hardware executes the INIT command. The interface hardware clears the INIT bit after the command executes. |
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