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EB632 数据表(PDF) 8 Page - Freescale Semiconductor, Inc |
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EB632 数据表(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 112 page  Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 8 Freescale Semiconductor Reset SCDIS 6 0 SC140 Disabled Enables/disables the SC140. This bit cannot be changed after reset. 0 = SC140 enabled 1 = SC140 disabled ISPS 7 0 Internal Space Port Size Defines the initial value of BCR[ISPS]. This bit must be set in order to use the host interface. Setting ISPS configures the MSC8103 to respond to accesses from a 32-bit external master to its internal space. This bit cannot be changed after reset. 0 = 60x-compatible data bus is 64 bits wide 1 = 60x-compatible data bus is 32 bits wide (lower 32 bits; upper 32 bits reserved for HDI16 IRPC 8–9 0 Interrupt Pin Configuration Defines the initial value of SIUMCR[IRPC]. DPPC 10–11 0 Data Parity Pin Configuration Defines the initial value of SIUMCR[DPPC]. NMI OUT 12 0 NMI OUT Defines the host core to handle a non-maskable Interrupt (NMI) event. 0 = NMI is serviced by SC140 core 1 = NMI is routed to external pin and serviced by the external host ISB 13–15 0 Initial Internal Space Base Select Defines the initial value of IMMR(ISB[0–14]) and determines the base address of the internal memory space and the DSPRAM base address on the local bus. Note that the SC140 core internal address space spans from 0x00000000 –0x00FFFFFF (16 MB). Therefore it is not advisable to map the Internal Memory Map Register (IMMR) in this space, since the SC140 core cannot access the registers of the SIU and CPM. QBus banks are mapped to address 0x00F00000, so using ISB value 101 causes the Dual-Port RAM (DPRAM) address space and the QBus address space to overlap. Modifying the QBus Base Registers to another address allows the user to access the DPRAM address space. ISB Internal Memory DSPRAM (Bank 10) 000 0xF0000000 0x02000000 001 0xF0F00000 0x03000000 010 0xFF000000 0x04000000 011 0xFFF00000 0x05000000 100 Reserved Reserved 101 0x00F00000 0x07000000 110 0x0F000000 0x08000000 111 0x0FF00000 0x09000000 Note: The 2K87M mask adds the DSPRAM location to the areas controlled by these bits. — 16 0 Reserved. Write to zero for future compatibility. BBD 17 0 Bus Busy Disable Defines the initial value of SIUMCR[BBD]. MMR 18–19 0 Mask Masters Requests Defines the initial value of SIUMCR[MMR]. — 20–21 0 Reserved. Write to zero for future compatibility. TCPC 22–23 0 Transfer Code Pin Configuration Defines the initial value of SIUMCR[TCPC]. BC1PC 24–25 0 BC1PC Value Defines the initial value of SIUMCR[BC1PC]. SWDIS 26 0 Software Watchdog Disable Defines the initial state of the Software Watchdog Timer 0 = Software Watchdog Timer enabled 1 = Software Watchdog Timer disabled Note: This field is undefined in the 2K42A mask set. DLLDIS 27 0 DLL Disable Defines whether the DLL mechanism is disabled. 0 = No DLL bypass 1 = DLL bypass MODCK_H 28–30 0 MODCK High Order Bits High-order bits of the MODCK bus, which determine the clock reset configuration. — 31 0 Reserved. Write to zero for future compatibility. Table 7. MSC8103 2K87M Mask Set Hard Reset Configuration Word Bit Descriptions (Continued) Name Reset Description Settings |
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