EB632 datasheet(53/112 Pages) FREESCALE

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CPM

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

•

Internal Rate (Sub Rate). In this mode, the FCC supplies only four PHY devices that have four distinct

addresses. Each channel is controlled by a dedicated hardware timer that is programmed and tuned to the data

rate needed. When a timer expires, a valid cell is sent to the corresponding PHY. The PHY sends idle cells to

keep its synchronization and transmission rate. The same is true for the TC. Once activated with FCC2 in this

mode, the TC requests cells and sends idle cells (UR interrupts can be disabled by clearing TCMODE[URE])

until a valid cell is transferred via the UTOPIA bus from the FCC. See Figure 24.

Operation in byte aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly. In this mode, once the TC is

enabled, it waits for the first Txsyn pulse to start transmit the first byte of the first cell. This ensures that subsequent

Txsyn pulses are byte-aligned to the cell boundaries.

Figure 23. TC Operation in FCC External Rate Mode

Figure 24. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)

FCC

PHY

MSC8103

DPR

UTOPIA

2M Cell Rate

2M Serial Rate

Keep FCC FIFO full

Generate Idle Cells

cell_req

BTM

ATM Channels

Idle Cell

ATM Cell

(External Rate)

FCC

PHY

DPR

UTOPIA

1M Cell Sub Rate

2M Serial Rate

1M Sub Rate

Generate Cell Req

BRG

cell req

Generate Idle Cells

BTM

ATM Channels

Idle cell

ATM cell

(Internal/Sub Rate)

Write to FIFO

ATM Cells Only

MSC8103

EB632 数据表(PDF) 53 Page - Freescale Semiconductor, Inc

EB632 数据表(HTML) 53 Page - Freescale Semiconductor, Inc

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