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EB632 数据表(PDF) 69 Page - Freescale Semiconductor, Inc |
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EB632 数据表(HTML) 69 Page - Freescale Semiconductor, Inc |
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69 / 112 page  Errata Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 Freescale Semiconductor 69 CPM64 AAL5 RxBD[LNE] error generated if PDU length exceeds 65512 bytes Date Added: 5/31/2001 Description: When the CPM receives an AAL5 PDU between 65512-65535 bytes (maximum length) the CPM sets the RxBD[LNE] indicating a receive length error, however the memory buffer contents for the PDU are correct. Workaround: Receive AAL5 PDU less than 65512 bytes or use microcode patch. System Number: 7025 0K40A 1K42A 2K42A CPM65 SS7 Microcode in ROM does not function correctly Date Added: 8/5/2001 Description: The SS7 microcode in ROM does not function correctly and should not be used. Workaround: Use the Enhanced SS7 microcode package. 0K40A 1K42A 2K42A CPM71 CPM does not snoop MCC buffer descriptors. Date Added: 8/5/2001 Description: When the MCC performs a DMA read or write of the buffer descriptor, GBL is not asserted and TC2 is always driven low.Therefore cache snooping will not be enabled for MCC BDs, therefore BDs in memory will not match the data cache. Also the bus used for the DMA is always the 60x, therefore if the BDs are on the local bus then the DMA consumes bandwidth on both the 60x and Local bus. Workaround: If GBL and/or TC2 are set in the MCC TSTATE/RSTATE parameters, use mi- crocode patch available from Freescale which fixes the above problem. If GBL and TC2 are not set to improve performance move the MCC BDs to the 60x bus. The microcode patch will fix both the GBL/TC2 and the bus performance issue. System Number: 7018 0K40A 1K42A 2K42A CPM72 MCC Global Underruns Date Added: 8/5/2001 Description: An MCC transmitter global underrun (GUN) error may result from intensive activ- ity on FCC1 (e.g.burst of short back to back Ethernet frames).This is due to the prioritization of the MCC transmitter relative to FCC1 receiver and transmitter as well as the MCC receiver. Workaround: Each serial channel above can request a service at normal or emergency level. In case of emergency, the request is handled before normal (non-emergency) request of the channels at a higher priority level.The proposed change is to allow the MCC transmitter to assert an emer- gency request instead of normal request. The impact on FCC1 in this case is minimal.This feature will controlled by a new MCC mode bit in future MSC8101 revisions. This new MCC mode bit will allow users to continue to use the current CPM priority scheme in their applications if re- quired. 0K40A 1K42A 2K42A CPM73 SI RAM Corruption Date Added: 8/5/2001 Description: (7049)An access to the SI RAM bank from the 60x bus while the corresponding TDM is active may result in data corruption within the SI RAM. Workaround: Associate the SI RAM bank with an inactive TDM before attempting to access it. Once the accesses has been made, the SI RAM bank should be re-assigned to the active TDM. System Number: 7049 0K40A 1K42A 2K42A Table 48. Errata Resolved in Mask Set 2K87M (Continued) Errata Number Errata Description Applies to Mask |
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