EB632 datasheet(13/112 Pages) FREESCALE

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Boot

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

5.7

I2C Clocking

The MSC8103 I

2C interface accesses the serial EPROM using a clock frequency derived by dividing the core

frequency by 4000. This division sets the I2C clock to 75 KHz or less, a clock frequency that most EPROMs

support. If the MSC8103 I2C gets an NAK during transmission, that is, the EPROM does not respond to the address

asserted by MSC8103, the boot loader stops execution. If the software watchdog timer is enabled, the counter will

eventually expire causing a system reset. After reset, the bootloading process restarts.

5.8

Reset Configuration Word

The only reset configuration mode that can be used while serial boot mode is enabled is reduced configuration

word. In the reduced configuration word, only the NMI_OUT, ISB, SWDIS, and DLLDIS fields can be set. For

details, see Section 4.1.2.

5.9

Default Programming During Boot

The bootloader routine provides default programming for parts of the MSC8103. The routine programs the UPMC

and the GPCM as required to support the internal SRAM and peripherals. The UPMC is programmed to support

the bus-to-CPM clock ratio. The routine checks the value of the SCMR[BUSDF] bits and selects the bus-to-CPM

clock ratio. The routine also programs the correct values for the ELIR[A–F] registers in the programmable interrupt

controller (PIC) to determine the interrupt mode (edge-triggered or level-triggered).

5.10 Multi-Processor Booting from a Serial EPROM

The I

2C protocol supports multi-master environments. All MSC8103 booting devices act as I2C masters and try to

access the serial EPROM. The first 14 bytes of the serial EPROM are reserved for an address table. Each master

accesses a different entry in the table according to its ISB[0–2] bits in the IMMR, allowing seven I2C masters in the

system. Each entry in the table contains the actual address where the boot program resides in the 2-byte increments.

The master accesses the table, reads the boot location address, and starts loading boot from there.If two or more

masters try to put information onto the bus, the first to produce a 1 when another produces a 0 loses the arbitration

(collision). If a collision occurs, the master that loses the arbitration retries.

Note:

If there are less than seven masters and not all 14 bytes of the table are needed, the boot code can start

inside the first 14 bytes of the table.

A MSC8103 I

2C master should access a table entry equal to its ISB[0–2] value multiplied by two. The bootloading

process always starts by accessing the address table. In a single master environment, the boot code may start

immediately after the address entry.

Note:

During the booting process, multiple masters should not address each other. There is no support for multi-

master errors.

5.11 Boot Code Changes

The boot code for the 2K87M mask set supports the I2C protocol. In addition, the code reflects changes in the

device design that fix a host checksum errata, make the SRAM base address ISB dependent, and allow the software

watchdog timer to be enabled or disabled via software. For a detailed listing of the updated boot code, see

Appendix A.

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