EB632 datasheet(2/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Summary of Differences

•

Interrupt system changes:

— CPM Low Interrupt Priority Registers (SCPRR_L and SCPRR_L_EXT) definitions

— Assignment of interrupt vector 44 to transmission convergence (TC) layer request

•

Debugging system changes:

— JTAG ID

— EOnCE Status Register (ESR) values

•

Removal of Enhanced Filter Coprocessor (EFCOP) support

•

Communications processor module (CPM) changes:

— RISC Controller Configuration Register (RCCR)

— Dual-port RAM

— Addition of ROM-based inverse multiplexing for ATM (IMA) microcode

— Addition of TC layer functionality to the time-slot assigner (TSA) with support through FCC2

— Addition of new MCC host commands

•

Errata

•

New bootloader program

Summary of Differences

Table 1 lists a summary of the differences between MSC8101 mask set 2K42A and MSC8103 mask set 2K87M.

Table 1. Difference Summary for MSC8101 Mask Set 2K42A and MSC8103 Mask Set 2K87M

Module

Function

MSC8101 Mask Set 2K42A

MSC8103 Mask Set 2K87M

System

Interface

Unit (SIU)

Internal Memory Map Register

(IMMR)

MASKNUM bit field = 0x02

MASKNUM bit field = 0x12

Internal Memory Map Mirror

Not supported

Added

Reset

Supported modes

Host reset and hardware reset

Host reset, hardware reset, and reduced

reset

Hardware reset configuration word

Seventeen fields defined

Eighteen fields defined--software

watchdog disable (SWDIS) bit added

Boot

Boot sources supported

From host (HDI16) or external memory

(system bus)

From host (HDI16), external memory

(system bus), or serial EPROM (I2C

interface)

Clock

Clock Scheme

Clock scheme configures SPLL PDF,

SPLL MF, and Bus DF

Clock scheme configures SPLL PDF,

SPLL MF, Bus DF, CPM DF, Core DF,

CPLL PDF, and CPLL MF

System Clock Mode Register

(SCMR)

Defines seven fields

Defines eight fields

System Clock Control Register

(SCCR)

Defines one field (DFBRG)

Defines two fields (CLKODIS and

DFBRG)

Clock modes

Two valid modes

Twenty-seven valid modes

CLKIN-to-CLKOUT delay

A function of frequency

Not a function of frequency

Enabling the DLL

DLL-enabled mode is not supported and

designs must use a zero-delay clock

buffer.

To enable the DLL, the zero-delay clock

buffer recommended for the 2K42A

mask set must be placed in PLL-bypass

mode or replaced.

Disabling the DLL

—

For clock modes 5, 6, 46, and 57, apply

offsets to DLL-disabled timing.

Maximum clock frequencies

BCLK/CLKOUT/SCLK = 68.75 MHz

CPMCLK = 137.5 MHz

DSPCLK = 275 MHz

BCLK/CLKOUT/SCLK = 100 MHz

CPMCLK = 200 MHz

DSPCLK = 300 MHz

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