CS5920 datasheet(5/160 Pages) AMCC

5 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

Base Class Code 0Bh: Processors ................................................................................................................. 48

Base Class Code 0Ch: Serial Bus Controllers ................................................................................................ 48

CACHE LINE SIZE REGISTER (CALN) ............................................................................................................... 49

Cache Line Size Register ................................................................................................................................ 49

LATENCY TIMER REGISTER (LAT) .................................................................................................................... 50

Latency Timer Register ................................................................................................................................... 50

HEADER TYPE REGISTER (HDR) ....................................................................................................................... 51

Header Type Register ..................................................................................................................................... 51

BUILT-IN SELF-TEST REGISTER (BIST) ............................................................................................................ 52

Built-In Self-Test Register ................................................................................................................................ 52

BASE ADDRESS REGISTER (BADR) ................................................................................................................. 53

Determining Base Address Size ...................................................................................................................... 53

Assigning the Base Address ............................................................................................................................ 53

Base Address Register - Memory .................................................................................................................... 54

Base Address Register - I/O ............................................................................................................................ 55

Base Address Register Response (Memory Assigned) to All-Ones Write Operation ..................................... 56

Read Response (I/O Assigned) to an All-Ones Write Operation to a Base Address Register ........................ 57

SUBSYSTEM VENDOR IDENTIFICATION REGISTER (SVID) ........................................................................... 58

Subsystem Vendor Identification Register ....................................................................................................... 58

SUBSYSTEM ID REGISTER (SID) ....................................................................................................................... 59

Subsystem Identification Register ................................................................................................................... 59

EXPANSION ROM BASE ADDRESS REGISTER (XROM) ................................................................................. 60

Expansion ROM Base Address Register ......................................................................................................... 60

Read Response to Expansion ROM Base Address Register (after all ones written) ...................................... 61

INTERRUPT LINE REGISTER (INTLN) ................................................................................................................ 62

Interrupt Line Register ..................................................................................................................................... 62

INTERRUPT PIN REGISTER (INTPIN) ................................................................................................................ 63

Interrupt Pin Register ....................................................................................................................................... 63

MINIMUM GRANT REGISTER (MINGNT) ............................................................................................................ 64

Minimum Grant Register .................................................................................................................................. 64

MAXIMUM LATENCY REGISTER (MAXLAT) ...................................................................................................... 65

Maximum Latency Register ............................................................................................................................. 65

OPERATION REGISTERS .................................................................................................................................... 66

PCI BUS OPERATION REGISTERS .................................................................................................................... 66

Operation Registers - PCI Bus ........................................................................................................................ 66

OUTGOING MAILBOX REGISTER (OMB) ........................................................................................................... 67

Outgoing Mailbox ............................................................................................................................................. 67

PCI INCOMING MAILBOX REGISTER (IMB) ....................................................................................................... 68

Incoming Mailbox ............................................................................................................................................. 68

PCI MAILBOX EMPTY/FULL STATUS REGISTER (MBEF) ................................................................................ 69

Mailbox Empty/Full Status Register (MBEF) ................................................................................................... 69

Mailbox Empty/Full Status Register ................................................................................................................. 69

PCI INTERRUPT CONTROL/STATUS REGISTER (INTCSR) ............................................................................. 70

Interrupt Control Status Register ..................................................................................................................... 70

Interrupt Control Status Register ..................................................................................................................... 71

PCI RESET CONTROL REGISTER (RCR) ........................................................................................................... 72

CS5920 数据表(PDF) 5 Page - Applied Micro Circuits Corporation

CS5920 数据表(HTML) 5 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载