CS5920 datasheet(7/160 Pages) AMCC

7 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

PCI READ TRANSFERS ....................................................................................................................................... 98

Single Data Phase PCI Bus Read of S5920 Registers or Expansion ROM .................................................... 98

PCI WRITE TRANSFERS ..................................................................................................................................... 99

Burst PCI Bus Read Attempt to S5920 Registers or Expansion ROM ............................................................ 99

Burst PCI Bus Write of S5920 Registers ......................................................................................................... 99

Target-Initiated Termination ............................................................................................................................ 99

Target Disconnects .......................................................................................................................................... 99

Target Requested Retries ............................................................................................................................. 100

Figure 4a. Target Disconnect Example 1 ...................................................................................................... 100

Figure 4b. Target Disconnect Example 2 ...................................................................................................... 100

Target Aborts ................................................................................................................................................. 100

Target Latency ............................................................................................................................................... 101

Target Locking ............................................................................................................................................... 101

PCI Bus Access Latency Components .......................................................................................................... 101

Figure 5. Target-Initiated Retry ...................................................................................................................... 101

Figure 6. Engaging the LOCK# Signal .......................................................................................................... 101

Target Termination Type ............................................................................................................................... 102

PCI BUS INTERRUPTS ...................................................................................................................................... 103

PCI BUS PARITY ERRORS ................................................................................................................................ 103

Access to a Locked Target by its Owner ....................................................................................................... 104

Access Attempt to a Locked Target ............................................................................................................... 104

Error Reporting Signal ................................................................................................................................... 104

MAILBOX OVERVIEW ........................................................................................................................................ 105

FUNCTIONAL DESCRIPTION ............................................................................................................................ 105

Figure 1. PCI to Add-On Mailbox Register .................................................................................................... 105

Add-On to PCI Mailbox Register ................................................................................................................... 106

Mailbox Empty/Full Conditions ...................................................................................................................... 106

Mailbox Interrupts .......................................................................................................................................... 106

Add-On Outgoing Mailbox, Byte 3 Access .................................................................................................... 107

BUS INTERFACE ................................................................................................................................................ 107

PCI Bus Interface .......................................................................................................................................... 107

Add-On Bus Interface .................................................................................................................................... 107

8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 108

CONFIGURATION ............................................................................................................................................... 108

Mailbox Status ............................................................................................................................................... 108

Input/Output Mode (MDMODE=0) ................................................................................................................. 108

Input Mode (MDMODE=1) ............................................................................................................................. 108

Mailbox Interrupts .......................................................................................................................................... 110

Servicing a PCI Mailbox Interrupt (INTA# asserted): ..................................................................................... 111

ADD-ON LOCAL BUS INTERFACE ................................................................................................................... 113

ADD-ON INTERFACE SIGNALS ........................................................................................................................ 113

SYSTEM SIGNALS ............................................................................................................................................. 113

ADD-ON S5920 REGISTER ACCESSES ........................................................................................................... 113

Register Access Signals ................................................................................................................................ 113

S5920 General Register Accesses ................................................................................................................ 113

Read Operation Register ............................................................................................................................... 114

Write Operation Register ............................................................................................................................... 114

CS5920 数据表(PDF) 7 Page - Applied Micro Circuits Corporation

CS5920 数据表(HTML) 7 Page - Applied Micro Circuits Corporation

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