CS5920 datasheet(94/160 Pages) AMCC

94 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

Figure 44. Type 0 Configuration Write Cycles

EXPANSION BIOS ROMS

This section provides an example of a typical PC-com-

patible expansion BIOS ROM. Address offsets 040h

through 07Fh represent the portion of the external nv

memory used to boot-load the S5920 controller.

Whether the expansion ROM is intended to be execut-

able code is determined by the contents of the first

three locations (starting at offset 0h) and a byte check-

sum over the defined length. The defined length is

specified in the byte at address offset 0002h. Table 2

lists each field location by its address offset, its length,

its value, and description.

The following represents the boot-load image for the

S5920 controller’s PCI configuration register:

PCI CLK

FRAME#

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

IDSEL

12345

DEVSEL#

ADD

DATA

1011

BYTE EN

Table 50. PC Compatible Expansion ROM

Byte Offset

Byte Length (decimal)

Binary Value

Description

Example

55h

BIOS ROM signature byte 1

55h

AAh

BIOS ROM signature byte 2

AAh

variable

Length in multiples of 512 bytes

01h

variable

Entry point for INIT function.

7h-17h

variable

Reserved (application unique data)

18h-19h

variable

Pointer to PCI Data Structure

1Ah-3Fh

variable

user-defined

40h

Vendor ID

(see page 2-23)

10E8h

42h

Device ID

(see page 2-24)

5920h

44h

not used

xxh

45h

S5920 Special

Modes

(see page 2-89 and 2-129)

01h

46h

not used

xxxxh

48h

Revision ID

(see page 2-29)

00h

49h

class code

(see page 2-30)

FF0000h

4Ch

not used

xxh

4Dh

not used

xxh

4Eh

your header

type

(see page 2-37)

00h

4Fh

self-test, if

desired

(see page 2-38)

80h or 00h

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