CS5920 datasheet(71/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

Table 41. Interrupt Control Status Register

Bit

Description

31:24

Reserved. Always zero.

Interrupt Asserted. This read only status bit indicates that one or more of the three possible interrupt conditions

are present. This bit is the OR of the mailbox interrupt conditions described by Bits 17 and 16, as well as the OR

of the Add-On interrupt described in Bit 22 (if the Add-On Interrupt is Enabled with Bit 13). No PCI interrupt is

generated, nor is this bit ever set, for an Add-On Interrupt without the Add-On Interrupt Enable set.

Add-On Interrupt. This bit is set when the ADDINT# input pin is driven low by an Add-On bus device. A high bit

indicates an Add-On device is requesting service. In addition, if the ADDINT# Enable bit is set, the S5920 will

assert a PCI interrupt (INTA# driven low). The source driving ADDINT# must deassert this input before the PCI

interrupt (INTA#) is driven to a false state. Host software must clear the Add-On interrupt source before exiting

its interrupt handler routine.

21:18

Reserved. Always zero.

"PCI Incoming Mailbox Interrupt. This bit can be set when the mailbox is written by the Add-On interface. This bit

operates as read or write one clear. A write to this bit with the data of ""one"" will cause this bit to be reset; a

write to this bit with the data of ""O "" will not change the state of this bit."

"PCI Outgoing Mailbox Interrupt. This bit can be set when the mailbox is read by the Add-On interface. This bit

operates as read or write one clear. A write to this bit with the data of ""one"" will cause this bit to be reset; a

write to this bit with the data of ""O "" will not change the state of this bit."

15:14

Reserved. Always zero.

ADDINT# Enable. If this bit is high, the S5920 will allow the Add-On interrupt request to drive the INTA# pin. It

has no effect on the assertion of the Add-On Interrupt Bit 22.

Enable Incoming Mailbox interrupt. This bit allows a write from the incoming mailbox register byte identified by

bits 9 and 8 to produce a PCI interface interrupt. This bit is read/write.

11:10

Hardwired to 1. Reserved.

9:8

Incoming Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to actually cause the inter-

rupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/

write.

7:5

Reserved. Always zero.

Enable Outgoing Mailbox Interrupt. This bit allows a read by the Add-On of the outgoing mailbox register byte

identified by bits 1 and 0 to produce a PCI interface interrupt. This bit is read/write.

3:2

Hardwired to 1. Reserved.

1:0

Outgoing Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to actually cause the

interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is

read/write.

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