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CS5920 数据表(PDF) 65 Page - Applied Micro Circuits Corporation |
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CS5920 数据表(HTML) 65 Page - Applied Micro Circuits Corporation |
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65 / 160 page  S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 65 Data Book MAXIMUM LATENCY REGISTER (MAX- LAT) This register may be optionally used by bus masters to specify how often this device needs PCI bus access. A value of zero indicates that the bus master has no stringent requirement. The units defined by the least significant bit are in 250 ns increments. Since the S5920 is a PCI target device only, this register is treated as “information only” and has no further imple- mentation within this device. Figure 25. Maximum Latency Register Register Name: Maximum Latency Address Offset: 3Fh Power-up value: 00h, hardwired Boot-load: not used Attribute: Read Only Size: 8 bits 00h 0 7 Bit Value |
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