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STR91XF 数据表(PDF) 57 Page - STMicroelectronics |
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STR91XF 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 72 page ![]() STR91xF Electrical characteristics 57/72 Table 18. EMI write operation Notes: 1 ALE_LENGTH = 1 by default (can be programmed to be 2 by setting the bits In the SCU_SCR0 register) 2 WSTWR =1Fh by default (WR wait state time = WSTWR x tBCLK, WSTWR can be programmed in the EMI_WCRx Register) 3 WSTWEN= 0 by default (WR assertion delay from chip select. WSTWEN can be programmed in the EMI_WECRx Register) 4 When the CPU executes a 16-bit write to a x8 EMI bus, the second write cycle's address setup time is defined as tWAS=(WSTWEN - ½) x tBCLK Figure 13. Non-Mux Bus (8-bit) write timings Symbol Parameter Test Conditions Value Unit Typ tWCR WRn to CSn inactive tBCLK/2 ns tWP Write Pulse Width (WSTWR-WSTWEN+1) x tBCLK ns tWDS Write Data Setup Time (non-mux mode) (WSTWEN+1/2) x tBCLK ns Write Data Setup Time (mux mode ) ALE length=1 WSTWEN>2 (WSTWEN - 1.5) x tBCLK ALE length=2 WSTWEN>3 (WSTWEN - 2.5) x tBCLK tWDH Write Data Hold Time tBCLK/2 ns tWAS Write Address Setup Time (WSTWEN+1/2) x tBCLK 4) ns tWAH Write Address Hold Time tBCLK/2 ns tAW ALE pulse width (ALE_LENGTH) x tBCLK ns tAAH Address to ALE hold time tBCLK/2 ns tAAS Address to ALE setup time (ALE_LENGTH) x tBCLK ns tWCR tWAH tWDH tWP Address Data tWAS tWDS EMI_CSxn EMI_A[15:0] EMI_D[7:0] EMI_BWR_WRLn |
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