STR91XF datasheet(27/72 Pages) STMICROELECTRONICS

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STR91xF

Functional overview

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2.21

I2C interfaces with DMA

The STR91xF supports two independent I2C serial interfaces, designated I2C0, and I2C1.

Each interface allows direct connection to an I2C bus as either a bus master or bus slave

device (firmware configurable). I2C is a two-wire communication channel, having a bi-

directional data signal and a single-directional clock signal based on open-drain line drivers,

requiring external pull-up resistors.

Byte-wide data is transferred between a Master device and a Slave device on two wires. More

than one bus Master is allowed, but only one Master may control the bus at any given time.

Data is not lost when another Master requests the use of a busy bus because I2C supports

collision detection and arbitration. More than one Slave device may be present on the bus, each

having a unique address. The bus Master initiates all data movement and generates the clock

that permits the transfer. Once a transfer is initiated by the Master, any device that is addressed

is considered a Slave. Automatic clock synchronization allows I2C devices with different bit

rates to communicate on the same physical bus. A single device can play the role of Master or

Slave, or a single device can be a Slave only. A Master or Slave device has the ability to

suspend data transfers if the device needs more time to transmit or receive data.

Each I2C interface on the STR91xF has the following features:

●

Programmable clock supports various rates up to I2C Standard rate (100 KHz) or Fast rate

(400 KHz).

●

Serial I/O Engine (SIOE) takes care of serial/parallel conversion; bus arbitration; clock

generation and synchronization; and handshaking

●

Multi-master capability

●

7-bit or 10-bit addressing

2.21.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each I2C channel

for fast and direct transfers between the I2C bus and SRAM with little CPU involvement. Both

DMA single-transfers and DMA burst-transfers are supported for transmit and receive.

2.22

SSP interfaces (SPI, SSI, and Microwire) with DMA

The STR91xF supports two independent Synchronous Serial Port (SSP) interfaces, designated

SSP0, and SSP1. Primary use of each interface is for supporting the industry standard Serial

Peripheral Interface (SPI) protocol, but also supporting the similar Synchronous Serial Interface

(SSI) and Microwire communication protocols.

SPI is a three or four wire synchronous serial communication channel, capable of full-duplex

operation. In three-wire configuration, there is a clock signal, and two data signals (one data

signal from Master to Slave, the other from Slave to Master). In four-wire configuration, an

additional Slave Select signal is output from Master and received by Slave.

The SPI clock signal is a gated clock generated from the Master and regulates the flow of data

bits. The Master may transmit at a variety of baud rates, up to 24 MHz

In multi-Slave operation, no more than one Slave device can transmit data at any given time.

Slave selection is accomplished when a Slave’s “Slave Select” input is permanently grounded

or asserted active-low by a Master device. Slave devices that are not selected do not interfere

with SPI activities. Slave devices ignore the clock signals and keep their data output pins in

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