STR91XF datasheet(24/72 Pages) STMICROELECTRONICS

24 / 72 page

Functional overview

STR91xF

24/72

the host computer must have a static image of the code being executed for decompressing the

ETM9 data. Because of this, self-modified code cannot be traced.

2.17

Ethernet MAC interface with DMA

STR91xF devices in the 128-pin package provide an IEEE-802.3-2002 compliant Media

Access Controller (MAC) for Ethernet LAN communications through an industry standard

Medium Independent Interface (MII). The STR91xF requires an external Ethernet physical

interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is

connected to the STR91xF MII port using as many as 18 signals (see pins which have signal

names MII_* in Table 2).

The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI Physical

layer. The STR91xF MAC is responsible for:

●

Data encapsulation, including frame assembly before transmission, and frame parsing/

error detection during and after reception.

●

Media access control, including initiation of frame transmission and recover from

transmission failure.

The STR91xF MAC includes the following features:

●

Supports 10 and 100 Mbps rates

●

Tagged MAC frame support (VLAN support)

●

Half duplex (CSMA/CD) and full duplex operation

●

MAC control sublayer (control frames) support

●

32-bit CRC generation and removal

●

Several address filtering modes for physical and multicast address (multicast and group

addresses)

●

32-bit status code for each transmitted or received frame

●

Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words (32

bits each), and the receive FIFO is 16 words deep.

A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-

speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This

DMA channel includes the following features:

●

Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor

chain

●

Direct MAC to SRAM transfers of receive frames with the related status, by descriptor

chain

●

Open and Closed descriptor chain management

2.18

USB 2.0 slave device interface with DMA

The STR91xF provides a USB slave controller that implements both the OSI Physical and Data

Link layers for direct bus connection by an external USB host on pins USBDP and USBPN. The

USB interface detects token packets, handles data transmission and reception, and processes

handshake packets as required by the USB 2.0 standard.

The USB slave interface includes the following features:

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