STR91XF datasheet(28/72 Pages) STMICROELECTRONICS

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Functional overview

STR91xF

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high-impedance state when not selected. The STR91xF supports SPI multi-Master operation

because it provides collision detection.

Each SSP interface on the STR91xF has the following features:

●

Full-duplex, three or four-wire synchronous transfers

●

Master or Slave operation

●

Programmable clock bit rate with prescaler, up to 24MHz for Master and 4MHz for Slave

●

Separate transmit and receive FIFOs, each 16-bits wide and 8 locations deep

●

Programmable data frame size from 4 to 16 bits

●

Programmable clock and phase polarity

●

Specifically for Microwire protocol:

–

Half-duplex transfers using 8-bit control message

●

Specifically for SSI protocol:

–

Full-duplex four-wire synchronous transfer

–

Transmit data pin tri-stateable when not transmitting

2.22.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each SSP

channel for fast and direct transfers between the SSP bus and SRAM with little CPU

involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit

and receive. Burst transfers require that FIFOs are enabled.

2.23

General purpose I/O

There are up to 80 GPIO pins available on 10 I/O ports for 128-pin devices, and up to 48 GPIO

pins on 6 I/O ports for 80-pin devices. Each and every GPIO pin by default (during and just after

a reset condition) is in high-impedance input mode, and some GPIO pins are additionally

routed to certain peripheral function inputs. CPU firmware may initialize GPIO pins to have

alternate input or output functions as listed in Table 2. At any time, the logic state of any GPIO

pin may be read by firmware as a GPIO input, regardless of its reassigned input or output

function.

Bit masking is available on each port, meaning firmware may selectively read or write individual

port pins, without disturbing other pins on the same port during a write.

Firmware may designate each GPIO pin to have open-drain or push-pull characteristics.

All GPIO pins are 5V tolerant, meaning in they can drive a voltage level up to VDDQ, and can be

safely driven by a voltage up to 5.5V.

There are no internal pull-up or pull-down resistors on GPIO pins. As such, it is recommended

to ground all unused GPIO pins to minimize power consumption and noise generation.

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