STR91XF datasheet(31/72 Pages) STMICROELECTRONICS

31 / 72 page

STR91xF

Functional overview

31/72

only require 8 bits of address on an 8-bit multiplexed address/data bus, and have simple

read, write, and latch inputs as shown in Figure 5

To use all 24 address bits, the following applies: 8 bits of lowest-order data and 8 bits of

lowest-order address are multiplexed on port 8. On port 9, 8-bits of mid-order address are

multiplexed with 8 bits of data, but these 8 data values are always at logic zero on this port

during a write operation, and these 8 data bits are ignored during a read operation. An

external latch device (such as a ‘373 latch) is needed to de-multiplex the mid-order 8

address bits that are generated on port 8. Port 7 outputs the 8 highest-order address

signals directly (not multiplexed). The output signal on pin EMI_ALE is used to demultiplex

the signals on ports 8 and 9, and the polarity of EMI_ALE is programmable. The output

signal on pin EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is

the data read strobe.

●

8-bit non-multiplexed data mode (Figure 6): Eight bits of data are on port 8, while 16 bits

of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn is the

data write strobe and the output on pin EMI_RDn is the data read strobe.

Figure 4.

EMI 16-bit multiplexed connection example

EMI_AD0

STR91xx

16-BIT

DEVICE

EMI_AD1

EMI_AD2

EMI_AD3

EMI_AD4

EMI_AD5

EMI_AD6

EMI_AD7

EMI_AD8

EMI_AD9

EMI_AD10

EMI_AD11

EMI_AD12

EMI_AD13

EMI_AD14

EMI_AD15

EMI_ALE

EMI_RDn

EMI_BWR_WRLn

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

CHIP_SELECT

WRITE_LOW_BYTE

READ

ADDR_LATCH

P8.7

P8.6

P8.5

P8.4

P8.3

P8.2

P8.1

P8.0

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

EMI_A16

EMI_A17

EMI_A18

EMI_A19

EMI_A20

EMI_A21

EMI_A22

(1) EMI_A23

A16

A17

A18

A19

A20

A21

A22

A23

P7.7

P7.6

P7.5

P7.4

P7.3

P7.2

P7.1

P7.0

EMI_WRHn

WRITE_HIGH_BYTE

EMI_CS0n

EMI_CS1n

EMI_CS2n

EMI_CS3n

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