STR91XF datasheet(16/72 Pages) STMICROELECTRONICS

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Functional overview

STR91xF

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2.10.7 External memory interface bus clock (BCLK)

The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are synchronized

to the BCLK. The BCLK is derived from the HCLK and the frequency can be configured to be

the same or half that of the HCLK. The maximum BCLK frequency is 66MHz.

2.10.8 USB interface clock

Special consideration regarding the USB interface: The clock to the USB interface must operate

at 48 MHz and comes from one of three sources, selected under firmware control:

●

CCU master clock output of 48 MHz.

●

CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to

produce 48 MHz for the USB while the CPU system runs at 96MHz.

●

STR91xF pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly

source the USB while the CCU master clock can run at some frequency other than 48 or

96 MHz.

2.10.9 Ethernet MAC clock

Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface device

requires it’s own 25 MHz clock source. This clock can come from one of two sources:

●

A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xF. In this

case, the STR91xF must use a 25 MHz signal on its main oscillator input in order to pass

this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that

an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xF and

the external PHY device.

●

An external 25 MHz oscillator connected directly to the external PHY interface device. In

this case, the STR91xF can operate independent of 25 MHz.

2.10.10 Operation example

As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator

input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and

X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xF

output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB interface

at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the background

at 32.768 kHz, and the CPU can go to very low power mode dynamically by running from

32.768 kHz and shutting off peripheral clocks and the PLL as needed.

2.11

Flexible power management

The STR91xF offers configurable and flexible power management control that allows the user

to choose the best power option to fit the application. Power consumption can be dynamically

managed by firmware and hardware to match the system’s requirements. Power management

is provided via clock control to the CPU and individual peripherals.

Clocks to the CPU and peripherals can be individually divided and gated off as needed. In

addition to individual clock divisors, the CCU master clock source going to the CPU, AHB, APB,

EMI, and FMI can be divided dynamically by as much as 1024 for low power operation.

Additionally, the CCU may switch its input to the 32 kHz RTC clock at any time for low power.

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