Data Sheet

ADL5960

SPECIFICATIONS

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Rev. A | 5 of 32

Table 1. Specifications (Continued)

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY INTERFACES

AVCC, OVCC, OVDD

Supply Voltage (AVCC, OVCC)

4.75

5.0

5.25

V

Supply Current (AVCC + OVCC)

EN = AVCC, Register 0x20 = 0x0B (BYPASS = 0, LOMODE =

3)

200

225

250

mA

EN = AVCC, Register 0x20 = 0x1D (OFMODE = 3)

110

120

130

mA

EN = 0 V (shutdown)

32

2000

µA

SPI Supply Voltage (OVDD)

1.8

3.3

3.6

V

SPI Supply Current (OVDD)

2

24

500

µA

1 Error correction coefficient (e00) obtained from measurements of the ratio of reverse and forward IF output ports for short, open, and load terminations on RFOUT. Printed

circuit board (PCB) transmission line is de-embedded by splitting the measured transmission matrix of the through line on the PCB in half and incorporating one half into the

ideal model of the terminations. See the Calibration and Error Correction section for details.

2 Voltage gain from RF input to differential IF output, with high-impedance IF load. Although the FGAIN and RGAIN bit fields are seven bits wide, values beyond 0x42 are of

limited practical use because amplified noise starts to saturate the IF output drivers.

3 Second RF tone power = 0 dBm, frequency = fRF + 100 kHz.

4 Magnitude relative to the desired output at fIF = 500 kHz.

SERIAL INTERFACE TIMING SPECIFICATIONS

Figure 2. SPI Timing Diagram

Table 2. SPI Timing Specifications

Parameter

Description

Min

Typ

Max

Unit

tDS

Setup time between data and rising edge of SCLK

15

ns

tDH

Hold time between data and rising edge of SCLK

15

ns

tCLK

Clock period

150

ns

tS

Setup time between CS and SCLK

40

ns

tH

Hold time between CS and SCLK

40

ns

tHIGH

Minimum period that SCLK must be in a logic high state

75

ns

tLOW

Minimum period that SCLK must be in a logic low state

75

ns

tZ

Maximum time delay between CS deactivation and SDIO bus return to high

impedance

150

ns

tACCESS

Maximum time delay between falling edge of SCLK and output data valid for a read

operation

30

ns