ADL5960ACCZ-R2 datasheet(24/32 Pages) AD

24 / 32 page

Data Sheet

ADL5960

APPLICATIONS INFORMATION

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Rev. A | 24 of 32

Figure 63. Simplified Schematic of the Common-Mode Control Interface

LOP and LOM Interface

The LO interface can be driven differentially or single-ended. A dif-

ferentially driven LO with a well designed PCB layout (for example,

using a ground, signal, signal, ground coplanar waveguide) can

help to reduce LO signal radiated emission and unwanted coupling

to other nets in the system. The LOP and LOM inputs are internally

biased at AVCC/2. When driven single-ended, the internal 100 Ω

termination can be impedance matched using a 2:1 external balun.

Figure 64. Simplified LO Interface

OFP and OFM Interface

The offset frequency interface (OFP and OFM) is internally biased

at a common-mode level of 3.3 V, and must be AC-coupled to

an external signal source. The inputs can be driven differentially

or single-ended with one terminal AC-grounded with a high value

capacitor. A value of 10 nF or higher is recommended for a 400 kHz

input frequency.

Figure 65. Simplified Offset Frequency Interface

EN Interface

The chip is in shutdown if either the shutdown bit in DEVICE_CON-

FIG (Register 0x02, Bit 1) is set, or the EN pin is deasserted. An

internal 415 kΩ pull-down ensures the device is off (shut down) if

the pin is left floating.

Figure 66. Simplified Enable Interface

SYNC and SCK Interfaces

The SYNC and SCK interfaces are both high-impedance CMOS

logic input interfaces. As listed in Table 1, the logic high and logic

low levels are defined relative to the serial port supply interface,

OVDD. Both inputs are internally pulled low when left floating.

Figure 67. SYNC and SPI Clock Interface

The SYNC interface is used to synchronize all ADL5960 devices

in a system. A falling edge on this interface resets the frequency

dividers in the LO and OF interfaces to a known, predefined state.

All ADL5960 devices receive the negative SYNC edge before the

next edge on the LO or OF interface arrives. The SYNC pulse can

also be applied directly after power-on, before an LO and OF clock

are applied.

CS Interface

The CS interface controls the start and ending of the communica-

tion through the serial interface of the device. The SPI is active

when the voltage on CS represents logic low and is disabled when

the voltage on CS is logic high, as defined in Table 1. The input is

internally pulled high, disabling the SPI, when this pin is left floating.

Figure 68. SPI Chip Select Interface

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