ADL5960ACCZ-R2 datasheet(17/32 Pages) AD

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Data Sheet

ADL5960

THEORY OF OPERATION

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a frequency synthesizer. When Bit 4 in Register 0x20 is cleared

(disabling bypass mode), the LOMODE bit field in Bits[1:0] can be

used to program the LO multiplication factor, MLO as seen in the

following equation:

MLO=2LOMODE−1

(2)

That is, divide by 2, or multiply by 1, 2, or 4. To ensure that

the desired output signal downconverts at the desired IF output

frequency, fIF, the frequency supplied to the LO interface must meet

the following condition:

fLO= fRF±fIF/MLO

(3)

Note from Table 1 that the divide-by-two mode can only be used

for LO input frequencies up to 2.4 GHz, whereas the doubler and

quadrupler modes only operate from 2 GHz to 8 GHz and from

4 GHz to 8 GHz, respectively. The LO interface also contains high-

frequency filters that suppress the harmonics and subharmonics in

the multiplier outputs. The center frequency of these filters can be

programmed through Register 0x21 and Register 0x22.

OF INTERFACE

Further simplification of the VNA configuration can be achieved by

employing the differential offset frequency (OF) interface. In this

configuration, a single swept source can be used to drive the RF

and LO interfaces at the same frequency (zero frequency offset),

while the IF output frequency is set by the signal applied to the OF

interface. To enable the offset mixer, clear Bit 4 in Register 0x20

and program the OFMODE bit field in Bits[3:2]. The offset frequency

input interface, when enabled, contains a programmable divider

with ratios of 1, 2, and 4. The multiplication factor, MOF, is as shown

in Table 6.

Table 6. Offset Input Configuration

MOF

0.5

10 (default)

0.25

Dividers off

Not applicable

The IF output signal frequency, including the offset mixer, can be

represented as follows:

fIF=fRF−MLO×fLO+MOF×fOF

(4)

For a true zero-offset sweep the LO frequency therefore needs to

satisfy the following:

fLO=fRF/MLO

(5)

such that the first two terms of Equation 4 cancel out, and the IF

output frequency equals the following:

fIF=MOF×fOF

(6)

The setting MOF = 1/4 (OFMODE = 2) is particularly useful and

is the recommended OFMODE setting. When the OF interface is

driven by the ADC sample clock frequency, fs, it precisely centers

the IF output signal in the first Nyquist zone of the ADC, with four

time domain sample points per complete cycle of IF waveform. In

this mode, the discrete time nature of the IF waveform becomes

evident due to the divide-by-4 digital dividing of the offset input.

IF SIGNAL PATH

The IF output signal of the mixers is passed through low-pass filters

to remove unwanted mixing products and noise. The bandwidth of

these filters is SPI-programmable through Register 0x25. The same

bandwidth setting is applied to both ADL5960 IF channels.

The IF amplifiers that follow the low-pass filters have individually

SPI-programmable gain, adjustable in 6 dB steps. This programma-

ble gain enables optimal interfacing of both channels to the ADC

input dynamic range.

The IF output interfaces of the ADL5960 are suited to drive a wide

range of ADCs directly. To avoid aliasing of broadband noise, it

is recommended to insert a simple antialiasing filter as shown in

Figure 53.

Figure 53. Interfacing the ADL5960 to an ADC

Each of the differential IF output nodes are low source impedance.

For this reason, it is recommended to use series resistors when

necessary, such as for driving filters or highly capacitive loads or

cables, as shown on the test circuit.

MULTIPORT VECTOR NETWORK ANALYZER

The ADL5960 can also be used to create network analyzers con-

sisting of multiple ports, as shown in Figure 54. Each port connects

to one ADL5960 device, and RF switches route the RF signal to

one ADL5960 at a time. For optimum phase (and magnitude) accu-

racy, ensure the connections from the RF source to all ports are

equal in length. Further, terminate the RFIN ports of the ADL5960

devices with 50 Ω at all times, that is, when the RF source is

connected but also when the source is not connected to the port.

A suitable way to achieve this is by using an SPxT nonreflective

switch with the RF source connected to the pole. For VNAs with

many ports, a cascade of nonreflective (terminated) RF switches

can be used at the expense of larger insertion loss and potentially

increased frequency tilt. Note that the connections to the RF source

as drawn in Figure 54 are overly simplified, and do not by any

means follow the recommendations for an optimal layout of the

system.

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