NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

Register

number

D2

D1

D0

Name

Type

Function

01h

0

0

1

INVRT

read/write

Polarity inversion register

02h

0

1

0

BKEN

read/write

Bus-hold enable register

03h

0

1

1

PUPD

read/write

Pull-up/pull-down selector register

04h

1

0

0

CFG

read/write

Port configuration register

05h

1

0

1

OUT

read/write

Output port register

06h

1

1

0

MSK

read/write

Interrupt mask register

07h

1

1

1

INTS

read only

Interrupt status register

Table 4. Register summary...continued

7.4 Writing to port registers

Data is transmitted to the PCA9574 by sending the device address and setting the least significant bit to logic 0

(see Figure 5 for device address). The command byte is sent after the address and determines which register

will receive the data following the command byte. Each 8-bit register may be updated independently of the other

registers.

7.5 Reading the port registers

In order to read data from the PCA9574, the bus controller must first send the PCA9574 address with the least

significant bit set to a logic 0 (see Figure 5 for device address). The command byte is sent after the address and

determines which register will be accessed. After a restart, the device address is sent again but this time, the

least significant bit is set to logic 1. Data from the register defined by the command byte will then be sent by the

PCA9574. Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first

byte is read, additional bytes may be read using the auto-increment feature.

7.5.1 Register 0 - Input port register

This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined

as an input or an output by the Configuration register. Writes to this register will be acknowledged but will have

no effect.

The default ‘X’ is determined by the externally applied logic level.

Bit

Symbol

Access

Value

Description

7

I0.7

read only

X

6

I0.6

read only

X

5

I0.5

read only

X

4

I0.4

read only

X

3

I0.3

read only

X

2

I0.2

read only

X

1

I0.1

read only

X

0

I0.0

read only

X

determined by externally applied logic level

Table 5. Register 0 - Input port register (address 00h) bit description

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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