NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

O0.7

R/W

0*

6

O0.6

R/W

0*

5

O0.5

R/W

0*

4

O0.4

R/W

0*

3

O0.3

R/W

0*

2

O0.2

R/W

0*

1

O0.1

R/W

0*

0

O0.0

R/W

0*

reflects outgoing logic levels of pins defined as outputs by

Register 4

Table 10. Register 5 - Output port register (address 05h) bit description

7.5.7 Register 6 - Interrupt mask register

All the bits of Interrupt mask register are set to logic 1 upon power-on or software reset, thus disabling

interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

M0.7

R/W

1*

6

M0.6

R/W

1*

5

M0.5

R/W

1*

4

M0.4

R/W

1*

3

M0.3

R/W

1*

2

M0.2

R/W

1*

1

M0.1

R/W

1*

0

M0.0

R/W

1*

enable or disable interrupts

0 = enable interrupt

1 = disable interrupt (default value)

Table 11. Register 6 - Interrupt mask register (address 06h) bit description

7.5.8 Register 7 - Interrupt status register

This register is read-only. It is used to identify the source of interrupt.

Remark: If the interrupts are masked, this register will return all zeros.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

S0.7

read only

0*

6

S0.6

read only

0*

5

S0.5

read only

0*

4

S0.4

read only

0*

3

S0.3

read only

0*

identifies source of interrupt

Table 12. Register 7 - Interrupt status register (address 07h) bit description

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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