NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin

does not match the contents of the Input port register. Only a read of the Input port register that contains the

bit(s) image of the input(s) that generated the interrupt clears the interrupt condition.

7.10 Standby

The PCA9574 goes into standby when the I2C-bus is idle. Standby supply current is lower than 1.0 μA (typical).

8 Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data

line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor

when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see

Figure 7).

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Figure 7. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line

while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while

the clock is HIGH is defined as the STOP condition (P) (see Figure 8).

mba608

SDA

SCL

P

STOP condition

S

START condition

Figure 8. Definition of START and STOP conditions

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls

the message is the ‘controller’ and the devices which are controlled by the controller are the ‘targets’ (see

Figure 9).

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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