NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

7.5.4 Register 3 - Pull-up/pull-down selector register

When bus-hold feature is not selected and bit 1 of Register 2 is set to logic 1, the I/O port can be configured to

have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 will select a 100

kΩ pull-up resistor for that I/O pin. Setting a bit to logic 0 will select a 100 kΩ pull-down resistor for that I/O pin. If

the bus-hold feature is enabled, writing to this register will have no effect on pull-up/pull-down selection.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

P0.7

R/W

1*

6

P0.6

R/W

1*

5

P0.5

R/W

1*

4

P0.4

R/W

1*

3

P0.3

R/W

1*

2

P0.2

R/W

1*

1

P0.1

R/W

1*

0

P0.0

R/W

1*

configures I/O port pin to have pull-up or pull-down when bus-hold

feature not selected and bit 1 of Register 2 is logic 1

0 = selects a 100 kΩ pull-down resistor for that I/O pin

1 = selects a 100 kΩ pull-up resistor for that I/O pin (default value)

Table 8. Register 3 - Pull-up/pull-down selector register (address 03h) bit description

7.5.5 Register 4 - Configuration register

This register configures the direction of the I/O pins. If a bit in this register is set (written with logic 1), the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared

(written with logic 0), the corresponding port pin is enabled as an output. At reset, the device’s ports are inputs.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

C0.7

R/W

1*

6

C0.6

R/W

1*

5

C0.5

R/W

1*

4

C0.4

R/W

1*

3

C0.3

R/W

1*

2

C0.2

R/W

1*

1

C0.1

R/W

1*

0

C0.0

R/W

1*

configures the direction of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input (default value)

Table 9. Register 4 - Configuration register (address 04h) bit description

7.5.6 Register 5 - Output port register

This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register

4. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the

value that is in the flip-flop controlling the output selection,

not the actual pin value.

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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