NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

7.5.2 Register 1 - Polarity inversion register

This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set

(written with ‘1’), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a

‘0’), the Input port data polarity is retained.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

N0.7

R/W

0*

6

N0.6

R/W

0*

5

N0.5

R/W

0*

4

N0.4

R/W

0*

3

N0.3

R/W

0*

2

N0.2

R/W

0*

1

N0.1

R/W

0*

0

N0.0

R/W

0*

inverts polarity of Input port register data

0 = Input port register data retained (default value)

1 = Input port register data inverted

Table 6. Register 1 - Polarity inversion register (address 01h) bit description

7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to

logic 1 enables bus-hold feature for the I/O bank. In this mode, the pull-up/pull-downs will be disabled. Setting

the bit 0 to logic 0 disables bus-hold feature.

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins. Setting the bit 1 to logic

1 enables selection of pull-up/pull-down using Register 3. Setting the bit 1 to logic 0 disables pull-up/pull-downs

on the I/O pins and contents of Register 3 will have no effect on the I/O.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

E0.7

R/W

X

6

E0.6

R/W

X

5

E0.5

R/W

X

4

E0.4

R/W

X

3

E0.3

R/W

X

2

E0.2

R/W

X

not used

1

E0.1

R/W

0*

allows the user to enable/disable pull-up/pull-downs on the I/O pins

0 = disables pull-up/pull-downs on the I/O pins and contents of Register

3 will have no effect on the I/O (default value)

1 = enables selection of pull-up/pull-down using Register 3

0

E0.0

R/W

0*

allows user to enable/disable the bus-hold feature for the I/O pins

0 = disables bus-hold feature (default value)

1 = enables bus-hold feature

Table 7. Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit description

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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