NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

002aaa966

CONTROLLER

TRANSMITTER/

RECEIVER

TARGET

RECEIVER

TARGET

TRANSMITTER/

RECEIVER

CONTROLLER

TRANSMITTER

CONTROLLER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

TARGET

Figure 9. System configuration

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver

is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level

put on the bus by the transmitter, whereas the controller generates an extra acknowledge related clock pulse.

A target receiver which is addressed must generate an acknowledge after the reception of each byte. Also

a controller must generate an acknowledge after the reception of each byte that has been clocked out of the

target transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-

up time and hold time must be taken into account.

A controller receiver must signal an end of data to the transmitter by not generating an acknowledge on the

last byte that has been clocked out of the target. In this event, the transmitter must leave the data line HIGH to

enable the controller to generate a STOP condition.

002aaa987

S

START

condition

9

8

2

1

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from controller

Figure 10. Acknowledgement on the I2C-bus

9 Bus transactions

Data is transmitted to the PCA9574 registers using ‘Write Byte’ transfers (see Figure 11 and Figure 12).

Data is read from the PCA9574 registers using ‘Read Byte’ transfers (see Figure 13 and Figure 14).

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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