NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

Legend: * default value.

Bit

Symbol

Access

Value

Description

2

S0.2

read only

0*

1

S0.1

read only

0*

0

S0.0

read only

0*

Table 12. Register 7 - Interrupt status register (address 07h) bit description...continued

7.6 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9574 in a reset condition

until VDD has reached VPOR. At that point, the reset condition is released and the PCA9574 registers and state

machine will initialize to their default states. The power-on reset typically completes the reset and enables the

part by the time the power supply is above VPOR. However, when it is required to reset the part by lowering the

power supply, it is necessary to lower it below 0.2 V.

7.7 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9574 registers

and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH.

7.8 Software reset

The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a

specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that

there is no device hanging the bus.

The Software Reset sequence is defined as following:

1. A START command is sent by the I2C-bus controller.

2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I2C-bus

controller.

3. The PCA9574 device(s) acknowledge(s) after seeing the General Call address ‘0000 0000’ (00h) only. If the

R/W bit is set to logic 1 (read), no acknowledge is returned to the I2C-bus controller.

4. Once the General Call address has been sent and acknowledged, the controller sends 1 byte. The value

of the byte must be equal to 06h.The PCA9574 acknowledges this value only. If the byte is not equal to

06h, the PCA9574 does not acknowledge it. If more than 1 byte of data is sent, the PCA9574 does not

acknowledge anymore.

5. Once the right byte has been sent and correctly acknowledged, the controller sends a STOP command to

end the Software Reset sequence: the PCA9574 then resets to the default value (power-up value) and is

ready to be addressed again within the specified bus free time. If the controller sends a Repeated START

instead, no reset is performed. The I2C-bus controller must interpret a non-acknowledge from the PCA9574

(at any time) as a ‘Software Reset Abort’. The PCA9574 does not initiate a software reset.

7.9 Interrupt output (INT)

The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is

configured as an input and the interrupt on it is not masked. The interrupt is deactivated when the port pin input

returns to its previous state or the Input Port register is read. It is highly recommended to program the MSK

register, and the CFG registers during the initialization sequence after power-up, since any change to them

during Normal mode operation may cause undesirable interrupt events to happen.

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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