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ST72340 数据表(PDF) 14 Page - STMicroelectronics |
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ST72340 数据表(HTML) 14 Page - STMicroelectronics |
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14 / 191 page  ST72340, ST72344, ST72345 14/191 Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ST7 ICC protocol reference manual. 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh I2C I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register 00h 00h 00h 00h 00h 40h 00h R/W Read Only Read Only R/W R/W R/W R/W 005Fh Reserved area (1 byte) 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h I2C3SNS I2C3SCR1 I2C3SCR2 I2C3SSR I2C3SBCR I2C3SSAR1 I2C3SCAR1 I2C3SSAR2 I2C3SCAR2 I2C3SSAR3 I2C3SCAR3 I2C3SNS Control Register 1 I2C3SNS Control Register 2 I2C3SNS Status Register I2C3SNS Byte Count Register I2C3SNS Slave Address 1 Register I2C3SNS Current Address 1 Register I2C3SNS Slave Address 2 Register I2C3SNS Current Address 2 Register I2C3SNS Slave Address 3 Register I2C3SNS Current Address 3 Register 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W Read Only Read Only R/W R/W R/W R/W R/W R/W 0070h 0071h 0072h ADC ADCCSR ADCDRH ADCDRL A/D Control Status Register A/D Data Register High A/D Data Low Register 00h xxh 0000 00xxb R/W Read Only Read Only 0073h to 007Fh Reserved area (13 bytes) Address Block Register Label Register Name Reset Status Remarks |
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