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数据搜索系统，热门电子元器件搜索 |
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ST72340 数据表(PDF) 50 Page - STMicroelectronics |
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ST72340 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 191 page  ST72340, ST72344, ST72345 50/191 POWER SAVING MODES (Cont’d) Figure 34. AWUFH Mode Flow-chart Notes: 1. WDGHALT is an option bit. See option byte sec- tion for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific in- terrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 8, “Interrupt Mapping,” on page 40 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC reg- ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. RESET INTERRUPT 3) Y N N Y CPU MAIN OSC PERIPHERALS 2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU MAIN OSC PERIPHERALS I[1:0] BITS ON OFF XX 4) ON CPU MAIN OSC PERIPHERALS I[1:0] BITS ON ON XX 4) ON 256 OR 4096 CPU CLOCK DELAY WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 CYCLE AWU RC OSC ON AWU RC OSC OFF AWU RC OSC OFF HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=1) |
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