ST72340 datasheet(32/191 Pages) STMICROELECTRONICS

32 / 191 page

ST72340, ST72344, ST72345

32/191

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see short ext. Reset in Figure 17), the

signal on the RESET pin may be stretched. Other-

wise the delay will not be applied (see long ext.

Reset in Figure 17). Starting from the external RE-

SET pulse recognition, the device RESET pin acts

as an output that is pulled low during at least

tw(RSTL)out.

7.4.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

signal is held low until VDD is over the minimum

level specified for the selected fOSC frequency.

(see “OPERATING CONDITIONS” on page 154)

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

7.4.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 17.

The LVD filters spikes on VDD larger than tg(VDD) to

avoid parasitic resets.

Note:

It is recommended to make sure that the VDD sup-

ply voltage rises monotonously when the device is

exiting from Reset, to ensure the application func-

tions properly.

7.4.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 17.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

Figure 17. RESET Sequences

VDD

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

tw(RSTL)out

RUN

th(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN

RESET

SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

tw(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

DELAY

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