ST72340 datasheet(35/191 Pages) STMICROELECTRONICS

35 / 191 page

ST72340, ST72344, ST72345

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.5.3 Low Power Modes

7.5.3.1 Interrupts

The AVD interrupt event generates an interrupt if

the corresponding AVDIE Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

7.5.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS

Read/Write

Reset Value: 000x 000x (xxh)

Bit 7 = Reserved, must be kept cleared.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

goes from 0 to 1. The pending interrupt information

is automatically cleared when software enters the

AVD interrupt routine.

0: PDVD interrupt disabled

1: PDVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit goes from 0 to 1. Refer

to Figure 19 and to Section 7.5.2 for additional de-

tails.

0: VDD over VIT+(AVD) threshold

1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL reaches its operating fre-

quency.

0: PLL not locked

1: PLL locked

Bits 2:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

CAUTION: When the LVD is not activated with the

associated option byte, the WDGRF flag can not

be used in the application.

Mode

Description

WAIT

No effect on SI. AVD interrupts cause the

device to exit from Wait mode.

HALT

The SICSR register is frozen.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

AVD event

AVDF

AVDIE

Yes

PDVD

AVD

LVD

LOC

KED

WDG

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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