ST72340 datasheet(28/191 Pages) STMICROELECTRONICS

28 / 191 page

ST72340, ST72344, ST72345

28/191

7.1 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequen-

cy from the RC oscillator or the external clock by 4

or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena-

bled and the multiplication factor of 4 or 8 is select-

ed by 3 option bits. Refer to Table 4 for the PLL

configuration depending on the required frequency

and the application voltage. Refer to Section 15.1

for the option byte description.

Table 4. PLL Configurations

1) For a target ratio of x4 between 3.3V - 3.65V,

this is the recommended configuration.

Figure 14. PLL Output Frequency Timing

Diagram

When the PLL is started, after reset or wakeup

from Halt mode or AWUFH mode, it outputs the

clock after a delay of tSTARTUP.

When the PLL output signal reaches the operating

frequency, the LOCKED bit in the SICSCR register

is set. Full PLL accuracy (ACCPLL) is reached after

a stabilization time of tSTAB (see Figure 14 )

Refer to Section 7.5.4 on page 35 for a description

of the LOCKED bit in the SICSR register.

Caution: The PLL is not recommended for appli-

cations where timing accuracy is required.

Target Ratio

VDD

PLL Ratio

DIV2

x41)

2.7V - 3.65V

OFF

3.3V - 5.5V

OFF

4/8 x

freq.

LOCKED bit set

tSTAB

tLOCK

input

tSTARTUP

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