ST72340 datasheet(47/191 Pages) STMICROELECTRONICS

47 / 191 page

ST72340, ST72344, ST72345

47/191

POWER SAVING MODES (Cont’d)

Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user

may choose to clear all pending interrupt bits be-

fore executing the HALT instruction. This avoids

entering other peripheral interrupt routines after

executing the external interrupt routine corre-

sponding to the wake-up event (reset or external

interrupt).

9.5 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when MCC/RTC interrupt enable flag

(OIE bit in MCCSR register) is set and when the

AWUEN bit in the AWUCSR register is cleared

(See “Register Description” on page 51.)

The MCU can exit ACTIVE-HALT mode on recep-

tion of the RTC interrupt and some specific inter-

rupts (see Table 8, “Interrupt Mapping,” on page

40) or a RESET. When exiting ACTIVE-HALT

mode by means of a RESET a 4096 or 256 CPU

cycle delay occurs (depending on the option byte).

After the start up delay, the CPU resumes opera-

tion by servicing the interrupt or by fetching the re-

set vector which woke it up (see Figure 31).

When entering ACTIVE-HALT mode, the I[1:0] bits

in the CC register are cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wake-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

Note: As soon as active halt is enabled, executing

a HALT instruction while the Watchdog is active

does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

HALT mode

ACTIVE-HALT mode

ST72340 数据表(PDF) 47 Page - STMicroelectronics

ST72340 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载