ST72340 datasheet(27/191 Pages) STMICROELECTRONICS

27 / 191 page

ST72340, ST72344, ST72345

27/191

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components.

Main features

■ Clock Management

– 1 MHz high-accuracy internal RC oscillator

(enabled by option byte)

– 1 to 16 MHz External crystal/ceramic resona-

tor (enabled by option byte)

– External Clock Input (enabled by option byte)

– PLL for multiplying the frequency by 8 or 4

(enabled by option byte)

■ Reset Sequence Manager (RSM)

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) with

reset generation (enabled by option byte)

– Auxiliary Voltage Detector (AVD) with inter-

rupt capability for monitoring the main supply

(enabled by option byte)

Figure 13. Clock, Reset and Supply Block Diagram

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

RCCRH/RCCRL Register

Tunable

RC Oscillator

DIVIDER

OSC

1-16 MHz

OSC Option bit

DIVIDER

PLL 1MHz --> 8MHz

PLL 1MHz --> 4MHz

External Clock (0.5-8MHz)

RC Clock (1MHz.)

PLL Clock 8/4MHz

OSC, PLLOFF

OSCRANGE[2:0]

Option bits

Crystal OSC (0.5-8MHz)

PLLx4x8

OSC1

OSC2

fOSC2

MAIN CLOCK

CONTROLLER

WITH REAL TIME

CLOCK(MCC/RTC)

fCPU

8MHz

4MHz

1MHz

Option bit

DIVIDER*

DIV2EN

Option bit*

*not available if PLLx4 is enabled

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