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ST7FL15F1MATRE 数据表(PDF) 63 Page - STMicroelectronics |
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ST7FL15F1MATRE 数据表(HTML) 63 Page - STMicroelectronics |
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63 / 138 page  ST7L15, ST7L19 63/138 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) quently, these registers must be initialized again when break is removed. Figure 44. Block Diagram of One Pulse Mode Figure 45. One Pulse Mode Timing Diagram Figure 46. Dynamic DCR2/3 update in One Pulse Mode LTIC pin Edge Selection OPEDGE PWM3CSR Register OP_EN 12-bit AutoReload Register 2 12-bit Upcounter 2 12-bit Active DCR2/3 Generation PWM OP2/3 PWM2/3 OVF ATR2 CNTR2 LTIC PWM2/3 000 DCR2/3 000 DCR2/3 ATR2 000 OVF ATR2 DCR2/3 OVF ATR2 DCR2/3 CNTR2 LTIC PWM2/3 fcounter2 fcounter2 CNTR2 LTIC 000 fcounter2 (DCR2/3)old (DCR2/3)new DCR2/3 FORCE2 TRAN2 FFF (DCR3)old (DCR3)new ATR2 000 PWM2/3 extra PWM3 period due to DCR3 update dynamically in One Pulse mode. 1 |
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