ST7FL15F1MATRE datasheet(30/138 Pages) STMICROELECTRONICS

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ST7L15, ST7L19

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SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)

7.6.3 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS

Read/Write

Reset Value: 0110 0xx0 (6xh)

Bit 7 = Reserved (should be 0)

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR

adjust the RC oscillator frequency and to obtain an

accuracy of 1%. Refer to section 7.3 on page 22.

Bit 4 = WDGRF Watchdog Reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given in the following table.

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL reaches its operating fre-

quency.

0: PLL not locked

1: PLL locked

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (by reading). When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bits 1:0 = Reserved (should be 0)

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

PLL TEST REGISTER (PLLTST)

Read/Write

Reset Value: 0000 0000(00h)

Bit 7: PLLdiv2 PLL clock divide by 2

This bit is read or write by software and cleared by

hardware after reset. This bit divides the PLL out-

put clock by 2.

0: PLL output clock

1: Divide by 2 of PLL output clock

Refer to “Clock Management Block Diagram” on

page 23.

Note: Write of this bit is effective after two tCPU cy-

cles (if system clock is 8 MHz) or else one cycle (if

system clock is 4 MHz), that is, effective time is

250ns.

Bits 6:0: Reserved, must always be cleared.

Res

CR1

CR0

WDG

LOCKED

LVD

Res

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

PLLdiv2

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