ST7FL15F1MATRE datasheet(65/138 Pages) STMICROELECTRONICS

65 / 138 page

ST7L15, ST7L19

65/138

DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)

11.2.6 Register Description

TIMER CONTROL STATUS REGISTER

(ATCSR)

Read / Write

Reset Value: 0x00 0000 (x0h)

Bit 7 = Reserved, must be kept cleared

Bit 6 = ICF Input Capture Flag

This bit is set by hardware and cleared by software

by reading the ATICR register (a read access to

ATICRH or ATICRL will clear this flag). Writing to

this bit does not change the bit value.

0: No input capture

1: An input capture has occurred

Bit 5 = ICIE IC Interrupt Enable

This bit is set and cleared by software.

0: Input capture interrupt disabled

1: Input capture interrupt enabled

Bits 4:3 = CK[1:0] Counter Clock Selection

These bits are set and cleared by software and

cleared by hardware after a reset. They select the

clock frequency of the counter.

Bit 2 = OVF1 Overflow Flag

This bit is set by hardware and cleared by software

by reading the ATCSR register. It indicates the

transition of the counter CNTR1 from FFFh to

ATR1 value.

0: No counter overflow occurred

1: Counter overflow occurred

Bit 1 = OVFIE1 Overflow Interrupt Enable

This bit is read/write by software and cleared by

hardware after a reset.

0: Overflow interrupt disabled.

1: Overflow interrupt enabled.

Bit 0 = CMPIE Compare Interrupt Enable

This bit is read/write by software and cleared by

hardware after a reset. It can be used to mask the

interrupt generated when any of the CMPFx bit is

set.

0: Output compare interrupt disabled.

1: Output Compare interrupt enabled.

COUNTER REGISTER 1 HIGH (CNTR1H)

Read only

Reset Value: 0000 0000 (00h)

COUNTER REGISTER 1 LOW (CNTR1L)

Read only

Reset Value: 0000 0000 (00h)

Bits 15:12 = Reserved, must be kept cleared

Bits 11:0 = CNTR1[11:0] Counter Value

This 12-bit register is read by software and cleared

by hardware after a reset. The counter CNTR1 in-

crements continuously as soon as a counter clock

is selected. To obtain the 12-bit value, software

should read the counter value in two consecutive

read operations. The CNTRH register can be in-

cremented between the two reads, and in order to

be accurate when fTIMER =fCPU, the software

should take this into account when CNTRL and

CNTRH are read. If CNTRL is close to its highest

value, CNTRH could be incremented before it is

read.

When a counter overflow occurs, the counter re-

starts from the value specified in the ATR1 regis-

ter.

ICF

ICIE

CK1

CK0

OVF1 OVFIE1 CMPIE

Counter Clock Selection

CK1

CK0

OFF

fLTIMER (1ms timebase @ 8 MHz)

fCPU

CNTR1_

ST7FL15F1MATRE 数据表(PDF) 65 Page - STMicroelectronics

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