ST7FL15F1MATRE datasheet(51/138 Pages) STMICROELECTRONICS

51 / 138 page

ST7L15, ST7L19

51/138

ON-CHIP PERIPHERALS (cont’d)

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. This downcounter is free-

running: It counts down, even if the watchdog is

disabled. The value to be stored in the CR register

must be between FFh and C0h (see Table 12

.Watchdog Timing):

– The WDGA bit is set (watchdog enabled).

– The T6 bit is set to prevent generating an imme-

diate reset.

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Following a reset, the watchdog is disabled. Once

activated, it can be disabled only by a reset.

The T6 bit can generate a software reset (the

WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction

generates a Reset.

Table 12.Watchdog Timing

Notes:

1. The timing variation shown in Table 12 is due to

the unknown status of the prescaler when writing

to the CR register.

2. The number of CPU clock cycles applied during

the RESET phase (256 or 4096) must be taken

into account in addition to these timings.

11.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by the option

byte, the watchdog is always active and the

WDGA bit in the CR is not used.

Refer to the Option Byte description in section 15

on page 126.

11.1.4.1 Using Halt Mode with the WDG

(WDGHALT Option)

If HALT mode with Watchdog is enabled by the op-

tion byte (no watchdog reset on HALT instruction),

it is recommended before executing the HALT in-

struction to refresh the WDG counter, to avoid an

unexpected WDG reset immediately after waking

up the microcontroller (same behavior in ACTIVE

HALT mode).

11.1.5 Interrupts

None.

11.1.6 Register Description

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

Table 13. Watchdog Timer Register Map and Reset Values

fCPU = 8 MHz

WDG

Counter Code

min

(ms)

max

(ms)

C0h

FFh

127

128

WDGA

Address

(Hex.)

Label

765

4321

002Eh

WDGCR

Reset Value

WDGA

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