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ST7FL15F1MATRE 数据表(PDF) 41 Page - STMicroelectronics |
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ST7FL15F1MATRE 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 138 page ![]() ST7L15, ST7L19 41/138 POWER SAVING MODES (cont’d) Figure 28. AWUFH Mode Flowchart Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external in- terrupt). Refer to Table 5, “Interrupt Mapping,” on page 32 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 5. If the PLL is enabled by the option byte, it outputs the clock after an additional delay of tSTARTUP (see Figure 11). RESET INTERRUPT3) Y N N Y CPU MAIN OSC PERIPHERALS2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU MAIN OSC PERIPHERALS I[1:0] BITS ON OFF XX4) ON CPU MAIN OSC PERIPHERALS I[1:0] BITS ON ON XX4) ON 256 OR 4096 CPU CLOCK DELAY5) WATCHDOG ENABLE DISABLE WDGHALT1) 0 WATCHDOG RESET 1 CYCLE AWU RC OSC ON AWU RC OSC OFF AWU RC OSC OFF HALT INSTRUCTION (Active Halt disabled) (AWUCSR.AWUEN=1) 1 |
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