ST7FL15F1MATRE datasheet(68/138 Pages) STMICROELECTRONICS

68 / 138 page

ST7L15, ST7L19

68/138

DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)

Bits 11:0 = ICR[11:0] Input Capture Data

This is a 12-bit register which is readable by soft-

ware and cleared by hardware after a reset. The

ATICR register contains the captured value of the

12-bit CNTR1 register when a rising or falling edge

occurs on the ATIC or LTIC pin (depending on

ICS). Capture will only be performed when the ICF

flag is cleared.

BREAK ENABLE REGISTER (BREAKEN)

Read/Write

Reset Value: 0000 0011 (03h)

Bits 7:2 = Reserved, must be kept cleared

Bit 1 = BREN2 Break Enable for Counter 2 (forced

at high level in ROM devices)

This bit is read/write by software. It enables the

break functionality for Counter 2 if BA bit is set in

BREAKCR. It controls PWM2/3 if ENCNTR2 bit is

set.

0: No Break applied for CNTR2

1: Break applied for CNTR2

Bit 0 = BREN1 Break Enable for Counter 1 (forced

at high level in ROM devices)

This bit is read/write by software. It enables the

break functionality for Counter 1. If BA bit is set, it

controls PWM0/1 by default, and controls PWM2/3

also if ENCNTR2 bit is reset.

0: No Break applied for CNTR1

1: Break applied for CNTR1

TIMER CONTROL REGISTER2 (ATCSR2)

Read/Write

Reset Value: 0000 0011 (03h)

Bit 7 = FORCE2 Force Counter 2 Overflow (not

applicable to ROM devices)

This bit is read/set by software. When set, it loads

FFFh in the CNTR2 register. It is reset by hard-

ware one CPU clock cycle after Counter 2 over-

flow has occurred.

0: No effect on CNTR2

1: Loads FFFh in CNTR2

Note: This bit must not be reset by software

Bit 6 = FORCE1 Force Counter 1 Overflow (forced

at high level in ROM devices)

This bit is read/set by software. When set, it loads

FFFh in CNTR1 register. It is reset by hardware

one CPU clock cycle after Counter 1 overflow has

occurred.

0: No effect on CNTR1

1: Loads FFFh in CNTR1

Note: This bit must not be reset by software

Bit 5 = ICS Input Capture Shorted

This bit is read/write by software. It allows the AT-

timer CNTR1 to use the LTIC pin for long input

capture.

0: ATIC for CNTR1 input capture

1: LTIC for CNTR1 input capture

Bit 4 = OVFIE2 Overflow Interrupt 2 Enable

This bit is read/write by software and controls the

overflow interrupt of Counter 2.

0: Overflow interrupt disabled

1: Overflow interrupt enabled

Bit 3 = OVF2 Overflow Flag

This bit is set by hardware and cleared by software

by reading the ATCSR2 register. It indicates the

transition of the Counter 2 from FFFh to ATR2 val-

ue.

0: No counter overflow occurred

1: Counter overflow occurred

Bit 2 = ENCNTR2 Enable Counter 2 for PWM2/3

This bit is read/write by software and switches the

PWM2/3 operation to the CNTR2 counter. If this

bit is set, PWM2/3 will be generated using CNTR2.

0: PWM2/3 is generated using CNTR1.

1: PWM2/3 is generated using CNTR2.

Note: Counter 2 becomes frozen when the

ENCNTR2 bit is reset. When ENCNTR2 is set

again, the counter will restart from the last value.

000

BREN2 BREN1

FORCE

ICS

OVFIE2

OVF2

ENCNT

TRAN2 TRAN1

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