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AT80C51RA2-RLSIV 数据表(PDF) 2 Page - International Rectifier |
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AT80C51RA2-RLSIV 数据表(HTML) 2 Page - International Rectifier |
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2 / 85 page  2 4188E–8051–08/06 AT/TS8xC51Rx2 tates multiprocessor communication (EUART) and an X2 speed improvement mechanism. The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 VQFP44 1.4 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RA2 TS80C51RD2 0 0 0 0 256 768 512 1024 32 32 TS83C51RB2 TS83C51RC2 TS83C51RD2 16k 32k 64k 0 0 0 256 256 768 512 512 1024 32 32 32 TS87C51RB2 TS87C51RC2 TS87C51RD2 0 0 0 16k 32k 64k 256 256 768 512 512 1024 32 32 32 PLCC68 VQFP64 1.4 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RD2 0 0 768 1024 48 TS83C51RD2 64k 0 768 1024 48 TS87C51RD2 0 64k 768 1024 48 |
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