AT80C51RA2-RLSIV datasheet(40/85 Pages) IRF

40 / 85 page

4188E–8051–08/06

AT/TS8xC51Rx2

6.5

Interrupt System

The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1),

three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt.

These interrupts are shown in Figure 6-13.

WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority.

Thus the order in INT0, TF0, INT1, TF1, RI or TI, TF2 or EXF2, PCA.

Figure 6-13. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit

in the Interrupt Enable register (See Table 6-17.Table 6-18.). This register also contains a global

disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by

setting or clearing a bit in the Interrupt Priority register (See Table 6-18.) and in the Interrupt Pri-

ority High register (See Table 6-19.). shows the bit values and priority levels associated with

each combination.

The PCA interrupt vector is located at address 0033H. All other vector addresses are the same

as standard C52 devices.

IE1

High priority

interrupt

Interrupt

polling

sequence, decreasing from

high to low priority

Low priority

interrupt

Global Disable

Individual Enable

EXF2

TF2

TF0

INT0

INT1

TF1

IPH, IP

IE0

PCA IT

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