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AT80C51RA2-RLSIV 数据表(PDF) 54 Page - International Rectifier |
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AT80C51RA2-RLSIV 数据表(HTML) 54 Page - International Rectifier |
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54 / 85 page ![]() 54 4188E–8051–08/06 AT/TS8xC51Rx2 WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 9.2.3 Signature bytes The TS87C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in Section “Signature bytes”. 9.3 EPROM Programming 9.3.1 Set-up Modes In o r d e r to p r o g r a m a n d ve r i fy th e EPR O M o r to r e a d th e si g n a tu r e b y te s, th e TS87C51RB2/RC2/RD2 is placed in specific set-up modes (See Figure 9-1.). Control and program signals must be held at the levels indicated in Table 9-2. 9.3.2 Definition of Terms Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4, P3.5 respectively for A0-A15 (P2.5 (A13) for RB, P3.4 (A14) for RC, P3.5 (A15) for RD) Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals:ALE/PROG, EA/VPP. Table 9-2. EPROM Set-Up Modes Mode RST PSEN ALE/P ROG EA/VP P P2.6 P2.7 P3.3 P3.6 P3.7 Program Code data 1 0 12.75V 0 1 1 1 1 Verify Code data 1 0 1 1 0 0 1 1 Program Encryption Array Address 0-3Fh 1 0 12.75V 011 01 Read Signature Bytes 1 0 1 1 0 0 0 0 Program Lock bit 1 1 0 12.75V 1 1 1 1 1 Program Lock bit 2 1 0 12.75V 1 1 1 0 0 Program Lock bit 3 1 0 12.75V 1 0 1 1 0 |
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