AT80C51RA2-RLSIV datasheet(22/85 Pages) IRF

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4188E–8051–08/06

AT/TS8xC51Rx2

Reset Value = 0000 0000b

Bit addressable

Table 6-3.

T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

Bit

Number

Bit

Mnemonic

Description

7TF2

Timer 2 overflow Flag

Must be cleared by software.

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

6EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is

enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode

(DCEN = 1)

5RCLK

Receive Clock bit

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

4TCLK

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3EXEN2

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if

timer 2 is not used to clock the serial port.

2TR2

Timer 2 Run control bit

Clear to turn off timer 2.

Set to turn on timer 2.

1C/T2#

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: FOSC).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock

out mode.

0CP/RL2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2

overflow.

Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

T2OE

DCEN

AT80C51RA2-RLSIV 数据表(PDF) 22 Page - International Rectifier

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