WM8731SEDSSLASHR datasheet(52/63 Pages) WOLFSON

52 / 63 page

WM8731 / WM8731L

Production Data

PD Rev 4.3 August 2006

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode, frame sync + 2 data

packed words

10 = I

2S Format, MSB-First left-1

justified

01 = MSB-First, left justified

00 = MSB-First, right justified

3:2

IWL[1:0]

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

LRP

DACLRC phase control (in left, right

or I

2S modes)

1 = Right Channel DAC data when

DACLRC high

0 = Right Channel DAC data when

DACLRC low

(opposite phasing in I

2S mode)

DSP mode A/B select (in DSP mode

only)

1 = MSB is available on 2nd BCLK

rising edge after DACLRC rising edge

0 = MSB is available on 1st BCLK

rising edge after DACLRC rising edge

LRSWAP

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

0000111

Digital Audio

Interface

Format

BCLKINV

Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

USB/

NORMAL

Mode Select

1 = USB mode (250/272fs)

0 = Normal mode (256/384fs)

Base Over-Sampling Rate

BOSR

USB Mode

0 = 250fs

1 = 272fs

Normal Mode

0 = 256fs

1 = 384fs

5:2

SR[3:0]

0000

ADC and DAC sample rate control;

See USB Mode and Normal Mode

Sample Rate sections for operation

CLKIDIV2

Core Clock divider select

1 = Core Clock is MCLK divided by 2

0 = Core Clock is MCLK

0001000

Sampling

Control

CLKODIV2

CLKOUT divider select

1 = CLOCKOUT is Core Clock

divided by 2

0 = CLOCKOUT is Core Clock

WM8731SEDS/R 数据表(PDF) 52 Page - Wolfson Microelectronics plc

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