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WM8731SEDS/R 数据表(PDF) 16 Page - Wolfson Microelectronics plc |
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WM8731SEDS/R 数据表(HTML) 16 Page - Wolfson Microelectronics plc |
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16 / 63 page ![]() WM8731 / WM8731L Production Data w PD Rev 4.3 August 2006 16 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK ADCDAT ADCLRC DACDAT DACLRC WM8731 CODEC DSP ENCODER/ DECODER Note: ADC and DAC can run at different rates Figure 3 Master Mode Connection BCLK (Output) ADCDAT ADCLRC DAC/LRC (Outputs) t DL DACDAT t DDA t DHT t DST Figure 4 Digital Audio Data Timing – Master Mode Test Conditions AVDD, HPVDD, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from BCLK falling edge tDL 0 10 ns ADCDAT propagation delay from BCLK falling edge tDDA 0 15 ns DACDAT setup time to BCLCK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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