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WM8731SEDS/R 数据表(PDF) 15 Page - Wolfson Microelectronics plc |
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WM8731SEDS/R 数据表(HTML) 15 Page - Wolfson Microelectronics plc |
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15 / 63 page ![]() WM8731 / WM8731L Production Data w PD Rev 4.3 August 2006 15 MASTER CLOCK TIMING XTI/MCLK t XTIL t XTIH t XTIY Figure 1 System Clock Timing Requirements Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information XTI/MCLK System clock pulse width high tXTIH 18 ns XTI/MCLK System clock pulse width low tXTIL 18 ns XTI/MCLK System clock cycle time tXTIY 54 ns XTI/MCLK Duty cycle 40:60 60:40 XTI/MCLK t COP CLKOUT CLKOUT (DIV X2) Figure 2 Clock Out Timing Requirements Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information CLKOUT propagation delay from XTI/MCLK falling edge tCOP 0 10 ns |
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