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AS7331

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 62

Figure 57:

Update Time of the Status Register Bits, if Some Measurement Results Were not Picked up

The status bits STATUS:STANDBYSTATE and STATUS:POWERSTATE, always show the actual

status of the internal control signals for Standby and power down. In both cases, it can differ from the

actual set bits CREG3:SB and OSR:PD, due to the behavior of the control signals while a

measurement is in process. The reading of the 16-bit values of the output result registers always starts

with the least significant byte.

The measurement value TEMP at address 1h is a 12-bit value, but its higher 4 bits until 16 are filled

with 0h. For Measurement modes programmed with CREG1:TIME < 212, there is a TEMP result with a

lower resolution. If the SYND mode is used and the OUTCONV register is set inactive by

EG2:EN_TM = “0”, any temperature measurement is not possible. In case CREG2:EN_TM is

enabled (

“1”), the TEMP value is only valid for conversion times with ≥ 212 internal system clocks, fCLK,

represented by the OUTCONV register.

Power-on reset, software-reset or return to the Configuration state resets the complete output register

bank.

IDLE

MEASUREMENT 2

RESULTS 1

MEASUREMENT 1

CONFIGURATION

IDLE

TCONV

MRES1 …

MRES3

READY

STATE

I²C activity

RESULTS 2

TCONV

data

fetch

LDATA = ‚0'

NDATA = ‚0'

LDATA = ‚0'

NDATA = ‚1'

LDATA = ‚1'

NDATA = ‚1'

LDATA = ‚0'

NDATA = ‚0'

OSR = 83h

start (OSR:SS ← ‚1')

AS7331 数据表(PDF) 63 Page - OSRAM GmbH

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